Workshop 1A

Understanding the Rules for TV Band Devices
BEGINS AT 09:00

Tutorial 1B
Radio-In-The-Loop: Design Tools for Software Radios

Tutorial 1C
ETSI Reconfigurable Radio Systems (RRS)

Tutorial 1D
Migrating Legacy Radios to the SCA

Tutorial 1E

Open Component Portability Infrastructure (Open CPI)

Workshop 1F
Public Safety Communications Workshop

 Expert Lecture 4E
Equalization Techniques for Multipath Channels

Cognitive radio technologies are enabling dynamic spectrum access and interference suppression, and they will soon be transitioning into a wide range of commercial and defense wireless products and services.  The FCC’s TV “white spaces” decision and the DARPA WNaN and EPLRS-XF efforts are just a few examples.  Standards are beginning to emerge in 3GPP and IEEE that are integrating these technologies into “4G” and beyond.  Although these near-term prospects are very promising, there remain many more exciting areas in which advanced radio and networking technology will have a profound impact.  The impact will be felt in areas such as radio network robustness, spectrum efficiency, regulations and enforcement, dynamic spectrum access to additional “white spaces”, device and network performance, improved broadband user experiences and applications, etc.  This panel of expert “radio futurists” will discuss the new vistas for smarter and smarter radio technologies, the impact of these technologies on regulatory frameworks and business models, and the challenges that remain in moving forward at Internet speed.

Introductory Remarks provided by:The Honorable Meredith Atwell Baker, Commissioner, Federal Communications Commission

MODERATOR:  Dr. Douglas Sicker, Chief Technologist, Federal Communications Commission

PARTICIPANTS:

• Dr. Bruce Fette, Program Manager, Defense Advanced Research Projects Agency (DARPA)
• Dr. Paul Kolodzy, Kolodzy Consulting (former Chair, FCC Spectrum Policy Task Force)
• Dr. Preston Marshall, Director, Univ. of Southern California, Information Sciences Institute
• Dr. Joe Mitola,  VP for the Research Enterprise, Stevens Institute of Technology

Field Programmable Gate Arrays (FPGAs) traditionally have been a replacement for low volume Application Specific Integrated Circuits (ASICs). Recently FPGAs have emerged with large amounts of logic, memory, DSP, CPU, and connectivity components making them a full Multi Processor System On a Chip (MPSoC) system. Historically these devices have been difficult to program following a hardware (HDL) design methodology with difficult placement, wiring, and timing closure constraints. Thus programming FPGAs has historically been difficult.

Processors, in contrast, have historically been programmed in high level languages such as C. Compilers have been developed that efficiently map the high level language to optimized assembly code. Even special purpose DSP types such as fixed point arithmetic have recently been efficiently dealt with in C languages. Parallel compilation has even been effective for modern Vector/SIMD loop nests. However, except for certain special cases of multithreading loop nests, parallelization of arbitrary codes distributed across multiple processors remains difficult.

Historically, the time to develop applications in a Processor has generally been faster because the long iterative cycles of place/route/timing in an FPGA. Recently FPGA vendors have tried to reduce this gap with innovative programming environments, the use of libraries, and the incorporation of processors on the same FPGA fabric.

This panel will look at the costs, programmability, performance, power, and time-to-market of multiprocessor designs versus FPGAs in a shoot-out to see who will ultimately dominate future SDR platforms.

Organizer: Kees Vissers, Xilinx
Moderator: John Glossner, Sandbridge
Jeff Bier, BDTI (balance)

Tutorial 7F

ESSOR SDR Architecture – Motivation and Overview