SDR'10 Program at a Glance

(This is a preliminary program, subject to change. Please check back often for updates.)



Monday - November 29
18:00-20:00 Early Registration, Sponsored by Green Hills Software, Inc.
19:00-21:00 Technical Program Committee Appreciation Dinner
Tuesday - November 30
Time Track A Track B Track C Track D Track E Track F Track G
8:00-12:00 Registration

Workshop 1A

Understanding the Rules for TV Band Devices

Tutorial 1B
Radio-In-The-Loop: Design Tools for Software Radios

Tutorial 1C
ETSI Reconfigurable Radio Systems (RRS)

Tutorial 1D
Migrating Legacy Radios to the SCA

Tutorial 1E

Open Component Portability Infrastructure (Open CPI)

Workshop 1F
Public Safety Communications Workshop

12:00 Lunch
13:30 Conference Welcome: John Glossner, Sandbridge Technologies and Conference Chair
13:40 Keynote: Masiyuki Ariyoshi, Principal Researcher and Cognitive Radio Research Project Leader System Platforms Research Laboratories Central Research Laboratories, NEC Corporation
Keynote: Tom Stroup, CEO, Shared Spectrum Company, with Vern Farthingham, Chairman, CTB Group
15:00 Coffee Break
15:15-17:15 Session 2A
Session 2B
Cognitive Radio I
Session 2C
Education & Radio Challenge
Expert Lecture 2D
Air Interface Innovations Applicable to Cognitive Radio Systems
Workshop 2E
Open Source in Military and Commercial Wireless
Workshop 2F
 Public Safety Communications
Welcome Reception and Forum Awards at the Spy Museum
Sponsored by General Dynamics 
(Includes Tapas and Drinks)
Wednesday - December 1
Time Track A Track B Track C Track D Track E Track F Track G
8:30 Introduction to Day 2 and Announcements: John Glossner, Sandbridge Technologies and Conference Chair
8:40 Keynote: Julius Knapp, Chief, Office of Engineering and Technology, FCC
9:20 Break
9:50 Session 3A
Session 3B
Cognitive Radio II
Session 3C
Communications Signal Processing I
Workshop 3D
 Tutorial 3E
Tutorial 3F
Two-Thirds of SDR is SD
Tutorial 3G
A Graphical Approach to FPGA Programming
11:50 Lunch & Exhibits
13:45 Session 4A
System Implementation and Test I
Session 4B
Cognitive Radio III
Session 4C
Communications Signal Processing II
Workshop 4D

 Expert Lecture 4E
Equalization Techniques for Multipath Channels

Tutorial 4F
Rapid Prototyping Digital SCA-Based SDR Waveforms with OSSIE: Hands-On
Tutorial 4G
Extending the SCA to Meet International Security Needs
15:45 Coffee Break
Panel - The Future of Radio Technologies

Cognitive radio technologies are enabling dynamic spectrum access and interference suppression, and they will soon be transitioning into a wide range of commercial and defense wireless products and services.  The FCC’s TV “white spaces” decision and the DARPA WNaN and EPLRS-XF efforts are just a few examples.  Standards are beginning to emerge in 3GPP and IEEE that are integrating these technologies into “4G” and beyond.  Although these near-term prospects are very promising, there remain many more exciting areas in which advanced radio and networking technology will have a profound impact.  The impact will be felt in areas such as radio network robustness, spectrum efficiency, regulations and enforcement, dynamic spectrum access to additional “white spaces”, device and network performance, improved broadband user experiences and applications, etc.  This panel of expert “radio futurists” will discuss the new vistas for smarter and smarter radio technologies, the impact of these technologies on regulatory frameworks and business models, and the challenges that remain in moving forward at Internet speed.


Introductory Remarks provided by:The Honorable Meredith Atwell Baker, Commissioner, Federal Communications Commission

MODERATOR:  Dr. Douglas Sicker, Chief Technologist, Federal Communications Commission


  • Dr. Bruce Fette, Program Manager, Defense Advanced Research Projects Agency (DARPA)
  • Dr. Paul Kolodzy, Kolodzy Consulting (former Chair, FCC Spectrum Policy Task Force)
  • Dr. Preston Marshall, Director, Univ. of Southern California, Information Sciences Institute
  • Dr. Joe Mitola,  VP for the Research Enterprise, Stevens Institute of Technology
17:30-19:30 Exhibitors and "Technology Showcase"
19:30 GNU Radio Users Group, Sponsored by Ettus Research
Thursday - December 2
Time Track A Track B Track C Track D Track E Track F Track G
8:30 Introduction to Day 3 and Announcements: John Glossner, Sandbridge Technologies and Conference Chair
Keynote: Dick Lynch, Executive Vice President and Chief Technology Officer
Verizon Communications
9:20 Coffee Break
9:50 Session 5A
System Implementation and Test II
Tutorial 5B
Emerging Commercial Wireless and Cognitive Radio Standards
Session 5C
Waveform and Software Design I
Workshop 5D
Workshop 5E
SDR in Space I
Expert Lecture 5F
GNU Radio: Introduction and Computational Capabilities
Session 5G
11:50 Lunch & Exhibits
13:45 Session 6A
Session 6B
System Implementation and Test III
Session 6C
Workshop 6D
Workshop 6E
SDR in Space II
Tutorial 6F
SCA Next Rollout
15:45 Break
16:00 Keynote: Madan Jagernauth, Vice President, Wireless Marketing and Product Management, Huawei Technologies (Bio)
Keynote: Jörgen Lantto, Executive Vice President, Chief Technology Officer and Strategy
ST Ericsson


Panel Session: "Comparing FPGA + C compilers with multi-core technology" 

Field Programmable Gate Arrays (FPGAs) traditionally have been a replacement for low volume Application Specific Integrated Circuits (ASICs). Recently FPGAs have emerged with large amounts of logic, memory, DSP, CPU, and connectivity components making them a full Multi Processor System On a Chip (MPSoC) system. Historically these devices have been difficult to program following a hardware (HDL) design methodology with difficult placement, wiring, and timing closure constraints. Thus programming FPGAs has historically been difficult.

Processors, in contrast, have historically been programmed in high level languages such as C. Compilers have been developed that efficiently map the high level language to optimized assembly code. Even special purpose DSP types such as fixed point arithmetic have recently been efficiently dealt with in C languages. Parallel compilation has even been effective for modern Vector/SIMD loop nests. However, except for certain special cases of multithreading loop nests, parallelization of arbitrary codes distributed across multiple processors remains difficult.

Historically, the time to develop applications in a Processor has generally been faster because the long iterative cycles of place/route/timing in an FPGA. Recently FPGA vendors have tried to reduce this gap with innovative programming environments, the use of libraries, and the incorporation of processors on the same FPGA fabric.

This panel will look at the costs, programmability, performance, power, and time-to-market of multiprocessor designs versus FPGAs in a shoot-out to see who will ultimately dominate future SDR platforms.


Organizer: Kees Vissers, Xilinx
Moderator: John Glossner, Sandbridge
Jeff Bier, BDTI (balance)

Seungwon Choi, Hanyang Univ (GPUs)
Dave Kelf, Signmatix (programming)
Fanny Mlinarsky, octoScope (test and verification)
Chris Rowen, Tensilica (Multi core)
Kees Vissers, Xilinx (C tools + FPGA + small cores)
Sanjay Jinturkar, Ikanos Communications, Inc. (Compilers)


18:00-20:00 Wireless Innovation Forum Members Reception and Annual Meeting
Friday - December 3
Time Track A Track B Track C Track D Track E Track F Track G
8h30 Session 7A
Waveform and Software Design II
Session 7B
Session 7C
Spectrum, Regulatory, and Standards
Session 7D
Communications Signal Processing III
Expert Lecture 7E
Modem Tutorial

Tutorial 7F

ESSOR SDR Architecture – Motivation and Overview

10h30 Coffee Break
Keynote:Rich North, Technical Director, Joint Program Executive Office Joint Tactical Radio System (JPEO JTRS)
11:30 End Note, Conference Close and Satisfaction Survey Prize Drawing




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