SDR'10 Technology Showcase

Download a list of Demos and a map of the Exhibition Area


[Wednesday Evening]         [Thursday Lunch]


Wednesday Evening

Execution Time Monitoring and Real-Time Multi-Processing with the ALOE SDR Middleware

Ismael Gomez (Polytechnical University of Catalonia, Spain); Antoni Gelonch (Polytechnic University of Catalonia, Spain); Vuk Marojevic (Polytechnic University of Catalonia, Spain)


Monitoring waveform execution time in Software-Defined Radios is essential in modern multi-processor radios. The process of assigning computing resources to waveform components improves with the accuracy of waveform components resource demands. In shared-resource radio infrastructures, this feature is essential since it provides a mechanism for resource accounting while ensures that a client is unable to block another. Multi-processor platform must ensure, in addition, that data-flows from one processor to another do not violate end-to-end latency constraints. Moreover, modern iterative algorithms (LDPC, turbo-decoding, etc.) consume different resources as a function of the receiver EbNo or target QoS. Therefore, computing resource managers capable to measure resource consumption can potentially make a tighter adjustment of its decisions as a function of these environment variables (Cognitive Radio). The demo shows how the ALOE middleware is able to analyze computing resource consumption as well as ensure all waveform deadlines are met in a distributed multi-processor environment.


A SystemC Radio-in-the-Loop Modeling for Cognitive Radio Equipments 
Stephane Lecomte (Technicolor, France); Wassim Jouini (Supélec, France); Christophe Moy (Supelec, France); Pierre Leray (IETR/Supelec Campus de Rennes, France)


Introduction In the context of reconfigurable cognitive radio equipment it can be interesting to propose a high level modeling approach. The advantage is that the obtained model can be simulated in order to observe the impact of the cognitive cycle (including all three: sensing, decision making and reconfiguration) into the global operation of the system, far in advance of its effective implementation. According to the results of the simulation, it is then possible to modify the functional architecture or/and the hardware architecture in order to be compliant with the specifications of the system. The modeling part description is presented in the paper entitled "Multi-Level Modeling and Simulation of a Cognitive Radio Equipment" at the conference in the research and development papers track. 

Objectives The proposed demonstration offers the validation and the illustration of a modeling approach for cognitive radio equipment design, through a SystemC simulation of a transmitter and a receiver connected via a real RF channel using USRP boards. This demonstration consequently shows the new concept of "radio-in-the-loop" modeling for cognitive radio. 

Short presentation The demonstrator is a wireless transceiver composed of two main parts: a transmitter (Tx) and a receiver (Rx). Each part is subdivided into three sub-parts which use different technologies. Both Tx and Rx are reconfigurable and have been designed with HDCRAM management architecture [1]. The cognitive scenario is the following: " A sensor at the receiver's side evaluates some quality metric (for example BER or SNR); " A simple decision making process based on thresholds decides if the modulation order is correct (neither too high, nor too low for the measured SNR); " A reconfiguration process is activated to change the constellation order accordingly. The main functions of the transmitter and the receiver are modeled in untimed SystemC. The cognitive cycle supervision is done through HDCRAM in SystemC also. These two SystemC sub-models are generated from a UML model developed with MOPCOM methodology [2]. USRP boxes are used to connect Rx to Tx through the radio channel. Thus it is necessary to connect the SystemC model with the USRP card. For that the GNU radio environment provides the adaptation means between the data from SystemC to URSP card. The GNU radio adapter is connected with SystemC model through a local TCP link emulated by a socket. On the other side of GNU Radio processing, this adapter is communicated with URSP card via a USB link. During the demonstration, the transmission starts at a high SNR, in a QPSK modulation scheme. The level of amplification at transmitter (Tx) is decreased and the receiver (Rx) automatically detects the level under which reception is no more good enough. Then it sends and activates a constellation change at Tx and reconfigures itself so that the transmission comes back at a good quality of service again. An interactive view of the HDCRAM manager elements activations is available to observe the progress of the reconfiguration. 

References [1] L. GODARD, C. MOY, J. PALICOT, "An Executable Meta-Model of a Hierarchical and Distributed Architecture Management for the Design of Cognitive Radio Equipments", Annals of Telecommunications, Special issue on Cognitive Radio, vol. 64, pp.463-482, number 7-8, Aug. 2009. [2] S. LECOMTE, S. GUILLOUARD, C. MOY, P. LERAY and P. SOULARD, "A Co-design methodology based on model driven engineering for SDR equipments", SDR Forum, Washington, DC, USA, December 2009.


A Unified Platform for Communication System Design and Prototyping: An LTE MIMO Demonstration
Ian C. Wong (National Instruments, USA); Yong Rao (National Instruments, USA); Takao Inoue (National Instruments, USA); Wes McCoy (National Instruments, USA); Ahsan Aziz (Freescale Semiconductor, USA)


A development platform that unifies software, hardware, and radio system design aspects for SDR remains elusive. The challenges SDR platforms face include the need for custom prototyping hardware, discrete RF designs, VHDL/Verilog RTL development, C/DSP assembly programming, and creating I/O interface drivers. Consequently, large engineering teams that have expertise across the many disciplines of radio design and implementation, from communication and algorithm experts to hardware, software, analog, and RF engineers are typically needed in order to meet the stringent time-to-market requirements of modern radio systems. From both a cost and time-to-market savings standpoint, it is desirable to engage the algorithm experts early in the development cycle. At the same time, it is beneficial for the implementation-oriented engineer to understand the overall system performance, which includes all the practical aspects of radio design, such as the impact of radio impairments, overall system architecture, and software-hardware interaction, prior to the development of custom hardware. The availability of development platforms that address these issues can bring significant cost and time-to-market savings, and are thus highly valuable for the wireless industry as a whole.

In this demonstration, we elaborate on the National Instruments hardware and software solution for SDR development. The generic hardware architecture consists of a general purpose processor, FPGA, and tightly-integrated I/O. These elements are interconnected via a high-speed standard bus with extensions for triggering and synchronization, all of which are programmed within a unified system design environment called LabVIEW. LabVIEW is a graphical system design language that brings together various models of computation, e.g. data-flow, textual math (i.e. .m files), state charts, and C-language, and is capable of targeting a variety of computational platforms including desktop/embedded processors, DSPs, and FPGAs, while at the same time integrating real-time performance and I/O seamlessly with the computational aspects. The power of this flexible software design language, together with a diverse suite of computation and I/O hardware, provide a scalable and flexible SDR platform that delivers on the promise of a unified platform for the entire SDR design flow.

In order to highlight the power of the National Instruments hardware and software platform for SDR, we demonstrate a prototype of a 3GPP-LTE Frequency Division Duplex (FDD) mode MIMO downlink and SC-FDMA uplink system that was developed entirely within LabVIEW. The prototype demonstrates a closed-loop 2x2 MIMO over-the-air link with adaptive modulation and coding (AMC) that supports all of the LTE bandwidths from 1.4 MHz to 20 MHz. The prototype includes the complete RF and baseband physical layer signal processing chain for both the base station and mobile station, each of which resides in an NI PXIe-1075 industrial form-factor PCI-express based chassis. Each chassis includes a PXIe-8130RT embedded multi-core CPU running a real-time operating system, which handles the link control, higher-layer protocol software, and communication with an optional host PC via TCP-IP. The core high-rate physical layer processing functions are implemented in an NI PXIe-5641R Intermediate Frequency (IF) Transceiver module, which is an NI LabVIEW targetable FPGA board with integrated 2-input, 2-output IF ports. In the case of the transmitter, after generating the baseband signals in the FPGA, it is digitally upconverted to IF on the PXIe-5641R, and subsequently modulated onto a radio frequency carrier using the NI PXI-5610 2.7 GHz RF upconverter. In the case of the receiver, the NI PXI-5600 2.7 GHz RF downconverter performs the modulation of the RF signal down to IF. This IF signal is then fed into the IF transceiver PXIe-5641R for receiver signal processing. The physical layer processing blocks are developed using LabVIEW for Windows, LabVIEW Realtime, and LabVIEW FPGA. The partitioning is determined based on the realtime rate requirements and also the bandwidth of the PXI-express bus. The low-rate blocks in the transmit signal chain, namely bit generation, constellation mapping, data and pilot subcarrier multiplexing, and precoding for closed-loop MIMO are all done in the embedded real-time controller. The high-rate blocks including the turbo encoding, OFDM symbol generation (which includes IFFT and Cyclic Prefix extension), and sample rate conversion are done in the FPGA. Similarly on the receiver chain, timing synchronization, FFT, CP removal, frequency offset correction, channel estimation, MIMO processing, and turbo decoding are all done partly in the FPGA and partly in the realtime controller. The final constellation, packet error rate, and spectrum displays, in addition to other non-real-time operations like hardware configuration are done in the host PC.

It is important to note that this working prototype was implemented entirely by communications and signal processing algorithm experts, rather than hardware or software experts, within a matter of months. This is a testament to the potential cost and development-time benefits of a unified hardware and software platform that truly provides a software-defined approach to rapid wireless design and prototyping.


Multi-Ghz Platform for Software Defined Radio

Chen Chang (BEEcube Inc., USA)


Developed out of the Berkeley Wireless Research Center (BWRC) at University of California at Berkeley, the BEE3's high-speed multiple FPGA based platform allows for flexible algorithm and feature set definitions to fit mission critical needs. The BEE3 excels as a true real-time development and deployment platform for:

  • Software Defined Radio (SDR)
  • Signal Intelligence
  • Wireless (digital based RF) Algorithm Applications
As a result, the BEE3 has attracted leading industry companies worldwide such as Aerospace Corporation, L3 Communications, and Thales Group.

BEEcube's SDR Demonstration Our demonstration highlights BEE3 as an SDR prototyping platform - showing off our FPGA based continuous wideband vector signal generator, controlled by software in real-time via Wind River's VxWorks over Gigabit Ethernet, with carrier frequency tone sweeps ranging from 0 to 2GHz. BEE3's inherit I/Q 2Gsps DAC highlights BEE3's wideband capability. The BEE3 ADC expansion board simultaneously captured analog output with Data being displayed directly and integrated with Matlab(tm). BEE3's ADC can sample up to 3 GHz, offering a true direct RF sampling capability.

BEE3 Easy Algorithm Deployment

Coupled with high-speed I/O and infrastructure, the BEE3 system software allows algorithm designers without any RTL or implementation knowledge to easily program the target BEE3 system. BEEcube Platform Studio (BPS) is a system-level, hardware/software co-development environment on top of the MathWorks" Simulink® framework. BPS provides automatic generation of all platform specific hardware interfaces and corresponding software drivers. Months of engineering tasks to convert complex DSP algorithms to implementation can be achieved through BPS in a matter of days, all without requiring user knowledge of the low level FPGA implementation details, such as high speed I/O interfaces, timing closure, HW/SW interfaces, and IP integration issues.

BEE3 Hardware Meets All Your Changing Mission Critical Needs
  • Combined with the BEEcube's 3rd generation Xilinx Virtex-5 FPGA based hardware platform, the BEE3, the integrated BEEcube solutions enables a wide range of high-performance real-time implementations in multiple military and defense applications, including signal intelligence, signal warfare, software defined radio, MIMO communications, radar applications, and many more.
  • Advanced signal processing algorithm can be rapidly prototyped on the BEE3 system, running at hundreds or MHz clock rates, which directly interface to multi-GHz A/D and D/A converters. When it comes to deployment, the same design can be easily retargeted in the BEEcube Platform Studio (BPS) design environment to fit into various hardware platforms with different form factors, capabilities, and FPGA technologies.

Sora -- High Performance Software Radio Platform Based on PC Architecture 
Jiansong Zhang (Microsoft Research Asia, P.R. China); Kun Tan (Microosft Research Asia, P.R. China); Ji Fang (Beijing Jiaotong University, P.R. China); Yongguang Zhang (Microsoft Research Asia, P.R. China)


This demo shows Sora, a fully programmable software radio platform based on general-purpose processors. With Sora, developers can implement and experiment with high-speed wireless protocol stacks, e.g. IEEE 802.11a/b/g and LTE, on commodity PCs, using familiar programming environments with powerful tools on standard operating systems. In the demo, we first show a Sora-based demonstration radio system, called SoftWiFi. SoftWiFi is a full suite of 802.11a/b/g implementation that can seamlessly interoperate with commercial 802.11 NICs at all modulation rates, and achieves equivalent performance as commercial NICs at each modulation. Then, we show another application that performs spectrum analyzing based on Sora on a normal PC. We demonstrate that with proper software architecture and programming optimization, general purpose processors have sufficient processing power for many wireless processing tasks. We believe such processing power of GPPs will continue increasing with ever falling price driven by Moore's law and large market. Sora is now available for non-commercial use as Microsoft Software Radio Academic Kit.Our final goal is to make Sora a common research platform to the community to facilitate the experimental research in high-speed wide-band cognitive and wireless research.


Common Data Link Quad-band Relay
Benjamin Egg (fred harris and Associates, USA); fred harris (San Diego State Univ, USA)


The Common Data Link (CDL) system is an essential DoD asset that suffers significant performance and reliability losses due to multipath interference and fading, particularly in low Angle of Arrival (AoA) operating conditions. This work was undertaken to mitigate those losses via minimally-intrusive firmware updates of existing hardware, while ensuring continuous legacy compatibility. Emphasis is given to low AoA operations.

The Quad band Relay (QbR) architecture is a simple, yet powerful solution that utilizes existing hardware and additional CDL bandwidth to create link diversity. Utilizing an efficient frequency diversity architecture, link-loss due to multipath is significantly reduced. This is due to the fact the multipath losses are frequency dependent, and QbR's redundant transmissions have offset frequency centers transmitting encoded versions of the original legacy waveform.

Legacy systems communicate with QbR upgraded platforms seamlesslywithout hardware, software, or firmware modification. Furthermore, QbR upgraded systems receive the same transmission and are able to extract additional link gains via processing. An unmodified CDL system's default br45 (bit rate45 Mbps) filter bank rejects the redundancy of QbR, thus receiving a 100% legacy waveform. On the other hand, a QbR receiver's firmware selects the br274 filter path, allowing the legacy waveform and 3 diversity encoded waveforms to be digitized, demodulated, and combined into one final br45 data stream. Only the IF receiver filter bank selection changes, as far as the hardware is concerned. Upgrading the sea of current CDL hardware has been a key consideration in developing the QbR architecture, and the two enabling criteria which determine upgradability are: 1) The presence of a br274 filter path, and 2) sufficient processing power (FPGA size). The later requirement is likely satisfied if the system supports, or was originally designed to support the br274 waveform (regardless of br274 functionality).


LabVIEW Channel Emulator 
Fanny Mlinarsky (octoScope, USA); Samuel MacMullan (ORB Analytics, USA)


Fox is a software based channel emulator that models a wireless channel with up to 4x4 MIMO paths. While currently supporting 802.11n channel models, Fox can be extended to incorporate other channel models, including LTE and a variety of military or proprietary models. Fox operates in the LabVIEW environment and works on MIMO streams of IQ samples. The demo will show operation on IQ streams stored in files and will include a presentation explaining the background and theory of wireless channel modeling. We will overview the industry standard channel models, including 802.11n, ITU (pedestrian and vehicular), LTE, LTE-Advanced, 802.11ac, 802.11ad channel models. We will explain and demonstrate the statistical nature of channel models.


Demonstration of LTE OFDM Transmitter / Receiver with channel model IP core on Xilinx FPGA 
Amit Mane (Innovative Integration, USA)


The next generation 3GPP wireless standard long-term evolution (LTE) provides a leap in performance and a move to complete packet-based processing. In the physical (PHY) level of the LTE specification, specific challenges exist when dealing with higher data throughput rates, as well as the move to OFDM technology for data transmission. 

Innovative Integration has developed, and is in the processing of continuing to develop several new IPcore solutions to meet the demands of this new specification. With such blocks, it is critical not only to verify them as stand- alone blocks- but also to validate them in real systems with real-world data and channel conditions. 

The Transmitter in the IP core performs the function of converting the message bits into real I/Q data using the OFDM engine with windowing and filtering options. The Channel model in the IP core converts the I/Q data into real-world signals showing various effects such as multipath and fading. The receiver section performs the synchronization and the OFDM demodulation to recover the message bits. 

Our demonstration consists of verification of the LTE OFDM transmitter/receiver core using Innovative Integration's X5-400M board. Successful operation of the LTE OFDM core will be demonstrated under various channel conditions for a variety of transmission bandwidths, cyclic prefix and modulation schemes. 

Author: Amit Mane, Amit Mane is a senior Digital Design Engineer at Innovative Integration Inc since May 2003. His expertise include DSP algorithm development on FPGA, high speed digital system design based on popular bus architectures such as PCI, PCIe and cPCie. Amit holds a bachelors degree in Instrumentation and a M.S.E.E. from Texas Tech University. Amit may be reached at [email protected] | 1-805-578-4285



Thursday Lunch


High performance, small footprint NCO for communications applications
Frank Raffaeli (RF Instrumentaion, USA); Stephen Dark (National Instruments, USA)


SDR applications are becoming more demanding, increasing the need for both implementation efficiency and performance. An NCO (Numerically-Controlled Oscillator) is one of the fundamental building blocks for any frequency-agile Software-Defined Radio. This presentation reviews the detailed implementation of a high-performance NCO in a graphical programming language, LabView FPGA, and analyses the noise spectrum results, tuning speed, and FPGA footprint. Using a recursive algorithm, this NCO can achieve a close-in (100 Hz) phase noise of -120 dBc, a noise floor of -180 dBc, all without using any block memory.

In a live demo, attendees can get under the hood of a high-performance software-defined radio as we walk through the implementation using the NI Flex-RIO adapter module hardware and the high-performance NCO LabView FPGA firmware design.


Signal Intelligence using LabVIEW FPGA and Peer-to-Peer Streaming

Stephen Dark (National Instruments, USA); Jerry Lopato (National Instruments, USA)


Signal intelligence requires the acquisition, movement, and processing of massive amounts of data. In order to achieve this kind of performance, typically FPGAs have been employed for performance reasons. However, while FPGAs have great computational power, they require an unfamiliar programming paradigm shift from the traditional sequential based processor model. This is in addition to the many FPGA programming pitfalls including safe resets, clock crossings, and reset crossings that often plague the inexperienced FPGA developer. LabVIEW FPGA is a graphical FPGA programming tool that allows the algorithm developer to more easily express their design at a higher level of abstraction thus removing them away from the many low level FPGA details and potential pitfalls. While still programming parallel algorithms, LabVIEW FPGA provides a more intuitive graphical environment where parallelism is more easily understood and programmed. LabVIEW FPGA enables engineers at various levels of FPGA programming experience an integrated development environment where both the expected high level programmatic expressiveness of LabVIEW is available while still allowing FPGA experts to develop low level optimized IP. In addition, third party HDL IP can easily be integrated into this environment including the Xilinx CORE Generator IP included with LabVIEW FPGA. Coupled with LabVIEW, PXIe, RF Hardware, Flex-RIO, and LabVIEW Real-Time, LabVIEW FPGA provides an environment where a wide array of development, prototyping, and production signal intelligence systems are more easily achievable. 

This signal intelligence example demonstrates the wide potential of National Instruments' hardware and software platforms for developing systems with demanding hardware specifications and custom FPGA processing. This demonstration will show the platform's ability to 1) acquire three highly synchronized RF wireless channels, 2) stream wide bandwidth RF signals between hardware modules, 3) calculate real-time power spectrums, 4) detect signals of interest, 5) record the detected signals of interest to disk, 6) geo-locate the signal source, and 7) determine the signal's modulation standard. First, the signal will be acquired using three of National Instruments PXIe based VSAs. Next, using Peer-to-Peer streaming, data is transferred directly via DMA from the three VSAs to the FlexRIO for FPGA signal processing without the need for any host computer interaction. Then, the FlexRIO's Virtex 5 SX95T FPGA performs the various signal processing algorithms including DDC channelization, overlapped windowing and FFTs, signal detection, location triangulation, and blind modulation detection all programmed using LabVIEW FPGA. In addition, once a signal of interest is detected, the raw time-domain signal is logged to a RAID drive. Throughout this entire process, the host computer functions as the user interface that controls the FPGA based signal processing and displays various pieces of feedback.


Using MLM for Signaling: A Cognitive Radio Capability on the GNU Radio 
Jakub Moskal (Northeastern University, USA); Shujun Li (Northeastern University, USA); Mieczyslaw Kokar (Northeastern University, USA)


The Modeling Language for Mobility Work Group is developing a language (MLM) to be used by Cognitive Radios to exchange control (signaling) information. In particular, radios can use MLM to exchange information about themselves (their "knobs" and "meters") in order to achieve interoperability. This demonstration will show an initial implementation of this functionality on the GNU radio toolkit and Universal Radio Software Peripheral (USRP).


FPGA-based Multi-Element Antenna Beamforming System 
Rodger Hosking (Pentek, USA)


FPGAs are handling an increasing number of the intensive real-time signal processing tasks for communications and signal intelligence system. This demonstration system features an array of eight antennas receiving a signal from a portable transmitter source. Each antenna signal is amplified, translated to IF, and then digitized by an A/D converter. Each digitized IF channel is down converted to baseband and then adjusted with beamforming phase and gain coefficients. Finally, all eight channels are summed together. 

The A/D conversion, down conversion, phase and amplitude processing and summation operations are all performed on FPGA-based software radio modules in a highly scalable architecture to support any number of antennas. 

The resulting system effectively steers the antenna array to a specific angle of receptivity to support applications including direction finding, diversity receivers and cell sectoring for mobile telecom base stations. 

The operational demo system provides a live display of detection of the angle of arrival of the portable transmitter signal as it moves in front of the antenna array.


Hyper-processed FIR Filters 
Benjamin Egg (fred harris and Associates, USA); fred harris (San Diego State Univ, USA); Chris Dick (Xilinx, USA)


Increasing data rates and spectrally adaptive modulation techniques continue to drive analog-to-digital and digital-to-analog converter frequencies higher. A previously rare data processing phenomenon, generally isolated to surveillance and electronic warfare engineering teams, is becoming a general challenge Converter-to-Core Clock Cycle Inversion (C4I). As conversion rates climbed closer to the C4I boundary, the processing challenges were efficiently managed by distributing multiply and accumulate (MAC) functions over increasingly parallel paths. As the data conversion rate approaches the processing clock frequency, a linear filter's processing necessarily becomes more and more parallel, until the C4I boundary is reached, at which point the designer must choose between reducing bandwidth or extending their 2-dimensional (parallel) filters to a third dimensionhyper processed filter architectures. 

When data is not separable into multiple channels, nor can the bandwidth or data rate be reduced, hyper-processed filters manage the signal processing by re-arranging standard FIR filters into "doubly parallel" filter structures, or 3 dimensional filters. This class of filter efficiently operates without reducing bandwidth or limiting throughput. In addition, timing constraints can be relaxed significantly, substantially increasing designer productivity. The price is paid in additional silicon to support the growing cubic architecture; however, this is a desirable trade off as silicon prices drop according to Moore's Law.


OSSIE/GNU Radio Generic Component Demonstration

Duyun Chen (University of Pennsylvania, USA); Garrett Vanhoy (University of Arizona, USA); Marypat Beaufait (University of Michigan, USA); Carl B. Dietrich (Virginia Tech, USA)


A Generic Component (GC) was created to integrate OSSIE and GNU Radio (GR), two widely used open source development suites for Software Defined Radio (SDR). The GC is an OSSIE component which can encapsulate one or more GR blocks and provide the necessary data conversions to interface OSSIE I/O with the GR blocks. The GCs encapsulated GR blocks and the GR block properties can be reconfigured at runtime. The purpose of this demonstration is to show the functionality of the GC in addition to the distributed waveform capability of OSSIE applied to GR.


Low Cost Single Chip FPGA Based Software Defined Radio Platform

Joseph Enke (Johns Hopkins University, USA)


This demonstration provides a low cost generic VHDL based software defined radio platform implemented on a field programmable gate array. The platform reduces cost of a traditional software defined radio by using a truly single chip system-on-a-chip architecture implemented on a low cost Xilinx Spartan3A DSP FPGA. The single chip implements an analog to digital converter interface, digital down converter, demodulator, stereo digital to analog converter interface, and a soft core microprocessor for system control and debug. This single chip replaces analog and digital signal processors and microprocessors. The platform uses an undersampling technique to sample an intermediate frequency provided by the analog front end. This technique further reduces cost of the system by lowering the system sample rate and allowing the use of an ADC with a lower sample rate. It also allows the use of a low cost FPGA with a system architecture that utilizes extra clock cycles between samples to reuse FPGA DSP hardware blocks. The VHDL based architecture of the system allows for rapid development, highly reconfigurable, and highly reusable digital signal processing hardware and software. This single chip architecture allows the Xilinx ISE Design Suite tool chain to be used for all simulation, development, debugging, and deployment of system hardware, firmware, and software.

The platform is demonstrated by digitizing, down converting, demodulating, and analog converting a frequency modulated signal from a simple dipole antennae connected to an RF front end. The analog output signal is played through a set of headphones and recognized as the local radio station that the platform software is tuned to. The system software can be stepped through while simultaneously viewing the signal at various stages of the DSP hardware via the JTAG interface.

The system is demonstrated using an Ettus Research TVRX daughterboard as an analog front end with a simple dipole antennae connected, a Nu Horizons Spartan3A DSP development board with a high speed analog to digital converter and stereo digital to analog converter, and a pair of speakers. The demonstrations system costs under $200 and the author proposes that a system can be realized for less than $100.


Wireless Distributed Computing
Sahana Raghunandan (Virginia Tech, USA); Jeffrey Reed (Virginia Tech, USA)


With increase in demand for improved performance of computing systems, distributed paradigms have become ubiquitous. Specifically, in the absence of wired infrastructure or untethered operation, wireless distributed computing (WDC) can prove to be very effective in the execution of distributed algorithms for remote sensing, position location and computer vision, to name a few. The demonstration of the prototype test bed aims to provide an insight into the feasibility analysis, design tradeoffs and capabilities of WDC, enhanced by cognition at each radio node. One of the primary goals is to provide a test environment to investigate resource allocation techniques for efficient distributed image processing in the presence of variable channel conditions.

GNU Radio software distribution has been used as a baseline for development with the USRP hardware platform. The block diagram below gives an overview of the functional workflow of the system.







powered by MemberClicks